Faculty Development Program on “Workshop on Cadence EDA Tool “

FDP on “Workshop on Cadence EDA Tool”

EVENT NAME	FDP on “Workshop on Cadence EDA Tool”
Event Description	The Department of Electronics and Computer Science , SAKEC, in association with ENTUPLE TECHNOLOGIES Pvt & Ltd is organizing Faculty Development Program on “Workshop on Cadence EDA Tool” HIGHLIGHTS: Tool can be used in the following research areas. 3D-IC Design Advanced Node Arm-Based Solutions Cloud Solutions Low Power Mixed Signal Photonics RF / Microwave FULL CUSTOM DESIGN FLOW Introduction to VLSI System Design and Cadence Schematic Capture using Virtuoso Schematic Editor Functional Simulation using Spectre Schematic driven Layout Design using Virtuoso Layout Editor Physical Verification using Assura which includes DRC & LVS Parasitic Extraction using Quantus QRC Post Layout Simulation Generation of GDSII SEMI CUSTOM DESIGN FLOW Functional Verification flow using Incisive RTL Synthesis using Genus Physical Implementation using Innovus Physical Verification Generation of GDSII Date of Workshop : 29th and 30th January 2021. Time:10am to 2pm. Workshop Registration Fees:- Nil If any Query, please contact Nibha Desai – 9320210378 Aparajita Bera – 9833748985
Registration link	FDP on “Workshop on Cadence EDA Tool “